The present patent application claims the benefit of earlier Japanese Patent Application No. H11-327370 filed Nov. 17, 1999, the disclosure of which is entirely incorporated herein by reference.
1. Field of the Invention
This invention relates to a technique of automatic layout design applied to CAD for placement and routing. The invention also relates to a mask set and a semiconductor integrated circuit manufactured by the automatic layout design technique, and to a recording medium storing the automatic layout program.
2. Description of the Related Art
Along with the progress of LSI technologies, the circuit scale becomes larger and larger, and consequently, which causes increase of an amount of logical design computation. Such logical design is carried out making use of computers, which is known as CAD (Computer Aided Design).
In designing interconnection of basic horizontal and vertical lines in the orthogonal coordinate system on CAD, horizontal and vertical lines often terminate at an intersection of two or more orthogonal lines. If the horizontal lines and the vertical lines are formed in different layers in an actual semiconductor device, a via hole must be formed at the terminal portions of the metal lines to connect the horizontal and vertical lines three-dimensionally. Accordingly, a connection pattern corresponds to the via hole must be defined at a terminal of horizontal and vertical lines on CAD.
In general, if two basic orthogonal lines having an ordinary width W terminate at an intersection, terminal processing is carried out to extend the ends of the orthogonal lines by W/2.
FIG. 1 shows an example of terminal processing of the basic orthogonal lines of the minimum width. In FIG. 26A, a horizontal line 801 and a vertical line 803 meet each other at a terminal. In a CAD system, only the intersection point at which the center lines 802 and 804 of the respective lines cross each other is recognized as an intersection 808. The CAD does not recognize the overlap of two orthogonal lines at all.
If, in an actual semiconductor device, the horizontal line 801 is formed in a lower layer and the vertical line 802 is formed in an upper layer, these two lines must be connected three-dimensionally by a via contact. In this case, the CAD layout requires a connection pattern 805 (FIG. 1C) at the intersection of the two orthogonal lines 801 and 803. The connection pattern 805 consists of a bottom metal 801a, which is a part of the end portion of the line 801, a top metal 803a, which is a part of the end portion of the line 803, and an opening 807 (hereinafter, referred to as a xe2x80x9ccutxe2x80x9d) for connecting the top and bottom metals 803a and 801a. 
In an example shown in FIG. 1, the CAD recognizes two lines crossing each other, and accordingly, it is possible to define the connection pattern 805 at the intersection recognized by the CAD. However, if the two lines terminate in the state shown in FIG. 1A, the overlapped area between the horizontal line 801 and the vertical line 803 is very small. If a via hole is formed in an actual integrated circuit based on the layout shown in FIG. 1A, the lines of the upper and lower layers can not be reliably connected.
To overcome this problem, the ends of the horizontal and vertical lines 801 and 803 are extended by W/2, as shown in FIG. 1B, so that the end portion of the vertical line 803 lies completely on top of the end portion of the horizontal line 801. Then, the connection pattern 805 is placed on the overlapped area.
FIG. 1C illustrates a connection pattern 805 and a side view of a via hole formed in an actual integrated circuit. The connection pattern 805 is square because it is placed at the intersection of two basic orthogonal lines.
FIG. 2 illustrates another conventional example of terminal processing of two orthogonal lines. In this case, two wider orthogonal lines meet each other and terminate at the junction. Although the wide lines are treated at special lines in CAD, both of the horizontal line 811 and the vertical line 811 are extended by W/2, so that the end portions of these lines completely overlap each other, like in FIG. 1. Because the overlapped area is large, a connection pattern 805 having a plurality of cuts 817 is placed in the overlapped area.
It is easy for a CAD system to carry out the terminal processing to design interconnection consisting of only orthogonal lines in a orthogonal coordinate system, as shown in FIGS. 1 and 2.
However, as the configuration of semiconductor integrated circuits becomes finer and finer, a higher precision is required in every respect including a manufacture process and components of a semiconductor integrated circuit. In particular, a delay component caused by interconnection (or wiring) adversely affects the performance of the integrated circuit when the integrated circuit becomes finer. For this reason, it is an important subject how to reduce such delay in the integrated circuit.
Most of the delay components of interconnection are caused by a line resistance. The most effective way to reduce a line resistance is to reduce the line length. To this end, it has been proposed to use oblique lines, in addition to the basic orthogonal lines, to reduce the distance between two points in a semiconductor circuit. There is also a proposal to design a circuit layout using oblique lines on CAD. If using oblique lines in multi-layered integrated circuit, the shape and the forming process of via holes connecting basic orthogonal lines in a lower layer and oblique lines in an upper layer must be optimized.
The inventors of the present invention have proposed in Japanese Patent Application Nos. 10-176285 and 11-175930 a technique for greatly reducing a line resistance of oblique lines itself. This is achieved by setting the width and film thickness of the oblique line to {square root over (2)} times as large as those of the basic orthogonal lines. In these publications, the optimal shapes of via holes for connecting metal lines of different layers are also proposed in order to reliably guarantee the cross-sectional area of the cut. The inventors also proposed a tree-type clock supply path comprised of a combination of oblique lines and the basic orthogonal lines.
However, no proposal has been made on a terminal processing for treating a terminal junction of an oblique line and a horizontal (or vertical) line on CAD.
Accordingly, it is an object of the present invention to provide an automatic layout method, which allows a CAD system to easily carry out terminal processing for treating end portions of lines, including oblique lines.
It is another object of the invention to provide an exposure mask set formed by the automatic layout method and suitably used to manufacture a multi-layered integrated circuit with oblique interconnection.
It is still another object of the invention to provide a semiconductor integrated circuit having an oblique line configuration, which can achieve faster and more precise operations.
It is yet another object of the invention to provide a large scaled integrated circuit (LSI) having a clock supply structure utilizing oblique lines.
It is yet another object of the invention to provide an LSI, in which a plurality of blocks are integrated, each block being capable of operating fast and accurately, in synchronization with others.
It is yet another object of the invention to provide a method of manufacturing a semiconductor integrated circuit having an oblique interconnection structure.
It is yet another object of the present invention to provide a storage medium storing a program for executing an automatic layout method. By loading this program on a CAD, the CSD can generate a circuit layout using oblique lines with less data amount.
To achieve these objects, in one aspect of the invention, an automatic layout method used to, for example, CAD is provided. With this method, a first line having a first width is generated in a prescribed direction. Then, a second line having a second width is generated so that the second line extends at an oblique angle with respect to the first line and terminates at an end portion of the first line with an overlapped area between the first and second lines. Then, one or more VIA patterns are placed in the overlapped area so that one of them is located at an intersection of the longitudinal center lines of the first and second lines.
Preferably, the method further comprises the step of detecting if there are any unnecessary areas projecting from the overlapped area, and deleting the unnecessary areas if there are any. By deleting the unnecessary area projecting from the overlapped area, the wiring resources (i.e., effective areas on a semiconductor substrate) can be efficiently used.
If one or both of the first and second lines have the minimum line width of the lithography technique, a single connection pattern is set at the intersection. If neither the first or second line has the minimum width, then, multiple connection patterns are set inside the overlapped area. In the latter case, the data processing time and amount can be reduced because only the same connection pattern is repeatedly generated.
The connection pattern is a combination of parallelograms (including squares and rectangles). At least a pair of parallel sides of the parallelogram is parallel to either the first or second line. In addition, the first and second lines can be reliably connected in an actual device manufactured from the layout.
The connection pattern consists of, for example, a first parallelogram, which is the end potion of the first line, a second parallelogram, which is the end portion of the second line, and a cut square placed inside the overlapped area of the first and second parallelograms. In this context, a parallelogram includes a square and rectangle.
An assembled VIA pattern may be placed on the overlapped area if the overlapped area is relatively large. In this case, the assembled VIA pattern consists of a first parallelogram, which is the end portion of the first line, a second parallelogram, which is the end portion of the second line, and a set of cut squares in the overlapped area of the first and second parallelograms. One of the cut squares is located at the intersection of the first and second lines.
The first and second lines represent, for example, wiring patterns located in different layers of a semiconductor device. Alternatively, the first and second lines represent wiring patterns located in a same layer of a semiconductor device.
In another aspect of the invention, an exposure mask set used to manufacture a semiconductor device is provided. The mask set comprising at least a first mask having basic orthogonal line patterns, a second mask having aperture patterns for via holes, and a third mask having oblique line patterns. The aperture patterns of the second mask are aligned to the end portions of the orthogonal line patterns of the first mask. The oblique line patterns of the third mask extend at an oblique angle with respect to the orthogonal line patterns of the first mask. The end portions of the oblique line patterns are aligned to both the end portions of the orthogonal line patterns of the first mask and the aperture patterns of the second mask.
By using this mask set, a multi-layered wiring structure using oblique lines can be manufactured, in which upper-layer lines and lower-layer lines are reliably connected, while preventing waste of the wiring resources at each layer.
In still another aspect of the invention, a semiconductor integrated circuit having an oblique line structure, which is manufactured using the above-mentioned mask set, is provided.
One example of such integrated circuit comprises a first wiring layer including orthogonal line patterns with a first line width, an insulating layer placed on the first wiring layer, and a second wiring layer placed on the insulating layer and including oblique line patterns with a second line width. Via contacts penetrate through the insulating layer in order to connect the orthogonal line patterns of the first layer and the oblique line patterns of the second layers. The end portions of the oblique line patterns are positioned directly above the end portions of the orthogonal line patterns of the first wiring layer. The via contact connects the orthogonal line pattern and the oblique line pattern at the end portions of these line patters. The horizontal cross-section of the via contact is square, and is completely inside the end portion of a narrower line pattern.
The end portion of an orthogonal line may be connected to the end portion of an oblique line through one or more via contacts. In this case, one of the via contacts is located at the intersection of the center lines of the orthogonal line and the oblique line.
Another example of the oblique-line integrated circuit comprises a PLL (phase-locked loop circuit) located at a corner of a chip, a main clock supply line extending from the PLL toward the center of the chip. The main clock supply line extends obliquely with respect to the orthogonal coordinate axes of the chip, and a clock tree extends from the end of the main clock supply line. The clock tree consists of clock lines that symmetrically branch off in oblique directions with respect to the basic orthogonal coordinate axes.
This configuration allows the load capacitance to be balanced in the chip, and allows the PLL to supply clocks accurately at a high speed.
The clock tree is comprised of multiple layers, and clock lines located in a same layer extends in a same oblique direction. This arrangement can reduce variations in signal transfer.
Still another example of the oblique-line integrated circuit comprises a PLL located at a corner of a chip, and a clock mesh covering the entire area of the chip. The clock mesh consists of oblique lines extending at an oblique angle with respect to the orthogonal coordinate axes of the chip. The clock mesh is formed in a same layer, thereby allowing a clock to be supplied to elements in the chip quickly.
Still another example of the oblique-line integrated circuit comprises a clock mesh consisting of oblique lines extending at an oblique angle with respect to the orthogonal coordinate axes of a chip, and a root driver for driving the entire clock mesh. A main clock supply line extends from the root driver, and multiple sub-drivers are connected to the main clock supply line. The sub-drivers drive the oblique lines independently. This arrangement can reduce a delay and a skew in the circuit.
In still another aspect of the invention, an LSI comprises a main PLL positioned near the periphery of a chip of the integrated circuit, a base-clock supply line extending from the main phase-locked loop, and a plurality of random blocks arranged in the chip. The base-clock supply line supplies a base clock (or a global clock) at a lower frequency. Each of the random blocks has a clock driver cell connected to the base-clock supply line, and a clock tree consisting of oblique lines. The clock driver cell converts the base clock into a higher frequency clock, and supplies the higher frequency clock to elements inside the associated block via the clock tree.
The base-clock supply line extends across the chip in a direction parallel to an orthogonal coordinate axis of the chip, or alternatively, it extends across the chip in a direction oblique with respect to the orthogonal coordinate axes of the chip.
Another example of the LSI comprises a main PLL positioned near the periphery of a chip, a base-clock supply line extending from the main PLL, and a plurality of random blocks having oblique clock meshes. The base-clock supply line supplies base clocks at a relatively low frequency. Each random block has a clock driver cell connected to the base-clock supply line. The clock driver cell converts the base clock into a higher frequency clock and supplies the higher frequency clock to elements inside the block via the oblique clock mesh.
By using the clock mesh consisting of oblique lines, high-frequency clocks can be supplied to various elements scattered in the block at the shortest distance with little delay.
In still another aspect of the invention, a Method for manufacturing a semiconductor integrated circuit is provided. With this method, first metal lines extending in a prescribed direction are formed on a semiconductor substrate. Then, an insulating layer is formed over the first metal lines and the semiconductor substrate. Then, via holes are formed in the insulating layer. The via-holes penetrate through the insulating layer and reach the end portions of the first metal lines. The bottom of each via hole is completely inside the associated first metal line. Then, the via-holes are filled with a conductive material to form contacts. Finally, second metal lines extending at an oblique angle with respect to the first metal lines are formed on the insulating layer, so that the end portions of the second metal lines completely cover the top faces of the contacts.
In still another aspect of the invention, a storage medium storing an automatic layout program is provided. This program is used to operate a CAD for designing, for example, an LSI. The program comprises the following steps:
causing the CAD to generate a first line having a first width and extending in a prescribed direction and a second line having a second width and extending at an oblique angle with respect to the first line, each of the first and second lines having a longitudinal center line;
causing the CAD to detect an overlapped area, in which the end portion of the first line and the end portion of the second line meet each other;
causing the CAD to detect an intersection of the longitudinal center lines of the first and second lines inside the overlapped area; and
causing the CAD to read a connection pattern from a database based on the shape of the overlapped area, and to place the connection pattern at the detected intersection.
The storage medium includes, but are not limited to, external memory, a semiconductor memory, a magnetic disc, optical disc, an optomagnetic disc, a magnetic tape, and so on. Floppy diskette, CD-ROM, MO discs are also included in the storage medium. By installing the program into a CAD or other automatic layout design systems, a terminal area (or an overlapped area), at which an oblique line and an orthogonal line terminate, are treated with less data processing amount. In addition, the most suitable connection pattern is selected and placed at the terminal area, so that the oblique line and the orthogonal line are reliably connected in an actual device or circuit.